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Intel® 64 and IA-32 architectures software developer’s manual combined volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 | This document contains the following: Volume 1: Describes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures. Volume 2: Includes the full instruction set reference, A-Z. Describes the format of the instruction and provides reference pages for instructions. Volume 3: Includes the full system programming guide, parts 1, 2, 3, and 4. Describes the operating-system support environment of Intel® 64 and IA-32 architectures, including: memory management, protection, task management, interrupt and exception handling, multi-processor support, thermal and power management features, debugging, performance monitoring, system management mode, virtual machine extensions (VMX) instructions, Intel® Virtualization Technology (Intel® VT), and Intel® Software Guard Extensions (Intel® SGX). Volume 4: Describes the model-specific registers of processors supporting IA-32 and Intel® 64 architectures. |
Intel® 64 and IA-32 architectures software developer's manual documentation changes | Describes bug fixes made to the Intel® 64 and IA-32 architectures software developer's manual between versions. NOTE: This change document applies to all Intel® 64 and IA-32 architectures software developer’s manual sets (combined volume set, 4 volume set, and 10 volume set). |
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Intel® 64 and IA-32 architectures software developer's manual volume 1: Basic architecture | Describes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures. |
Intel® 64 and IA-32 architectures software developer's manual combined volumes 2A, 2B, 2C, and 2D: Instruction set reference, A-Z | This document contains the full instruction set reference, A-Z, in one volume. Describes the format of the instruction and provides reference pages for instructions. This document allows for easy navigation of the instruction set reference through functional cross-volume table of contents, references, and index. |
Intel® 64 and IA-32 architectures software developer's manual combined volumes 3A, 3B, 3C, and 3D: System programming guide | This document contains the full system programming guide, parts 1, 2, 3, and 4, in one volume. Describes the operating-system support environment of Intel® 64 and IA-32 architectures, including: Memory management, protection, task management, interrupt and exception handling, multi-processor support, thermal and power management features, debugging, performance monitoring, system management mode, virtual machine extensions (VMX) instructions, Intel® Virtualization Technology (Intel® VT), and Intel® Software Guard Extensions (Intel® SGX). This document allows for easy navigation of the system programming guide through functional cross-volume table of contents, references, and index. |
Intel® 64 and IA-32 architectures software developer's manual volume 4: Model-specific registers | Describes the model-specific registers of processors supporting IA-32 and Intel® 64 architectures. |
Document | Description |
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Intel® 64 and IA-32 architectures software developer's manual volume 1: Basic architecture | Describes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures. |
Intel® 64 and IA-32 architectures software developer's manual volume 2A: Instruction set reference, A-L | Describes the format of the instruction and provides reference pages for instructions (from A to L). This volume also contains the table of contents for volumes 2A, 2B, 2C, and 2D. |
Intel® 64 and IA-32 architectures software developer's manual volume 2B: Instruction set reference, M-U | Provides reference pages for instructions (from M to U). |
Intel® 64 and IA-32 architectures software developer's manual volume 2C: Instruction set reference, V-Z | Provides reference pages for instructions (from V to Z). |
Intel® 64 and IA-32 architectures software developer's manual volume 2D: Instruction set reference | Includes the safer mode extensions reference. This volume also contains the appendices and index support for volumes 2A, 2B, 2C, and 2D. |
Intel® 64 and IA-32 architectures software developer's manual volume 3A: System programming guide, part 1 | Describes the operating-system support environment of an IA-32 and Intel® 64 architectures, including: memory management, protection, task management, interrupt and exception handling, and multi-processor support. This volume also contains the table of contents for volumes 3A, 3B, 3C and 3D. |
Intel® 64 and IA-32 architectures software developer's manual volume 3B: System programming guide, part 2 | Continues the coverage on system programming subjects begun in volume 3A. Volume 3B covers thermal and power management features, debugging, and performance monitoring. |
Intel® 64 and IA-32 architectures software developer's manual volume 3C: System programming guide, part 3 | Continues the coverage on system programming subjects begun in volume 3A and volume 3B. Volume 3C covers system management mode, virtual machine extensions (VMX) instructions, and Intel® Virtualization Technology (Intel® VT). |
Intel® 64 and IA-32 architectures software developer's manual volume 3D: System programming guide, part 4 | Volume 3D covers system programming with Intel® Software Guard Extensions (Intel® SGX). This volume also contains the appendices and indexing support for volumes 3A, 3B, 3C, and 3D. |
Intel® 64 and IA-32 architectures software developer's manual volume 4: Model-specific registers | Describes the model-specific registers of processors supporting IA-32 and Intel® 64 architectures. |
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Intel® architecture instruction set extensions programming reference | This document covers new instructions slated for future Intel® processors. |
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The Intel® 64 and IA-32 architectures optimization reference manual provides information on current Intel microarchitectures. It describes code optimization techniques to enable you to tune your application for highly optimized results when run on current Intel® processors. | |
Intel® Xeon® Scalable Processor throughput and latency | Describes throughput and latency for Intel® Xeon® Scalable Processor. |
10th Generation Intel® Core™ Processor Instruction throughput and latency | Describes throughput and latency for 10th Generation Intel® Core™ Processor. |
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Intel® Xeon® Processor E7 Family Uncore Performance Monitoring Programming Guide |
Intel® Xeon® Processor E5 v2 and E7 v2 Product Families Uncore Performance Monitoring Reference Manual |
Intel® Xeon® Processor 7500 Series Uncore Programming Guide |
Intel® Xeon® Processor E5 and E7 v3 Family Uncore Performance Monitoring Reference Manual |
Intel® Xeon® Processor E5-2600 v2 Product Family Uncore Performance Monitoring Reference Manual |
6th Generation Intel® Core™ Processor Family Uncore Performance Monitoring Reference Manual |
Intel® Xeon® Processor Scalable Memory Family Uncore Performance Monitoring Reference Manual |
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Intel Analysis of Speculative Execution Side Channels | This document provides an overview of the variants along with related Intel security features. |
Speculative Execution Side Channel Mitigations | This document provides a detailed explanation of the security vulnerabilities and possible mitigations. |
Intel® 64 and IA32 Architectures Performance Monitoring Events | Performance monitoring events for Intel® processors. |
bfloat16 - Hardware Numerics Definition | This document describes the bfloat16 floating-point format. |
5-Level Paging and 5-Level EPT white paper | This document describes planned extensions to the Intel 64 architecture to expand the size of addresses that can be translated through a processor’s memory-translation hardware. |
MCA Enhancements in Intel® Xeon® Processors | This document describes Enhanced MCA Logging software architecture and associated flows. |
Timestamp-Counter Scaling for Virtualization | The information contained in this white paper has been merged into volume 3C of the Intel® 64 and IA-32 architectures software developer's manual. |
Intel® 64 architecture x2APIC specification | Extensions to the xAPIC architecture are intended primarily to increase processor addressability. The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendability for future Intel platform innovations. |
Intel® 64 and IA-32 architectures application note TLBs, paging-structure caches, and their invalidation | The information contained in this application note is now part of Intel® 64 and IA-32 architectures software developer's manual volumes 3A and 3B. |
Intel® carry-less multiplication instruction and its usage for computing the GCM mode white paper | This paper provides information on the instruction, and its usage for computing the Galois Hash. It also provides code examples for the usage of PCLMULQDQ, together with the Intel® AES New Instructions (Intel® AES-NI) for efficient implementation of AES in Galois Counter Mode (AES-GCM). |
Intel® 64 architecture memory ordering white paper | This document has been merged into Volume 3A of Intel® 64 and IA-32 architectures software developer’s manual. |
Performance monitoring unit sharing guide | This paper provides a set of guidelines between multiple software agents sharing the PMU hardware on Intel® processors. |
Intel® Virtualization Technology FlexMigration (Intel® VT FlexMigration) application note | This application note discusses virtualization capabilities in Intel® processors that support Intel® VT FlexMigration usages. |
Intel® Virtualization Technology for Directed I/O architecture specification | This document describes the Intel® Virtualization Technology for Directed I/O. |
Intel® Scalable I/O Virtualization Technical Specification | This document describes Intel® Scalable I/O Virtualization, a scalable and composable approach for virtualizing I/O devices. |
Page Modification Logging for Virtual Machine Monitor white paper | The information contained in this white paper has been merged into volume 3C of the Intel® 64 and IA-32 architectures software developer's manual. |
Secure Access of Performance Monitoring Unit by User Space Profilers | This paper proposes a software mechanism targeting performance profilers which would run at user space privilege to access performance monitoring hardware. The latter requires privileged access in kernel mode, in a secure manner without causing unintended interference to the software stack. |